Compliance workshops , developer conferences, and interoperability test sessions are continually sponsored by PCI-SIG. These events leverage the popularity of PCIe to promote commonality in protocol testing among vendors. Locating and decoding protocol information using a PCI bus analyzer establishes more than just protocol compliance.
As a byproduct of physical layer protocol testing, a PCIe analyzer also determines how successfully data transfer is performed over a given link. Errors that might have resulted in field performance issues can be fully characterized and addressed prior to product release. Alternatives to PCIe protocol testing can be completed with traditional test tools like oscilloscopes. These options become more time consuming with each successive PCIe release.
An advanced PCI Express protocol analyzer with direct visibility into inline traffic is much more efficient and informative than indirect measurement of endpoint performance. Innovative PCIe analyzers provide a high return on investment by improving test efficiency and versatility. Downward compatibility is an essential PCIe protocol analyzer feature, with the release cadence for new PCIe iterations planned at two-year intervals. The best PCIe analyzers can accommodate link widths from lanes and data rates ranging from 2.
Memory size and segmentation for the capture of either long traces or multiple traces allows you to test PCI Express slot performance with more granularity and diagnostic prowess. Captured data can be recalled by the PCI Express analyzer to pinpoint the physical source of errors or defects. Interposer autotuning reduces test time by automatically detecting and adjusting for the correct PCIe parameters during test setup. Autotuning capabilities also improve the overall reliability and repeatability of the PCIe bus analyzer test.
Remote debugging is intended to address the rapid propagation of PCIe throughout the network computing landscape. Host-client connectivity features of PCI bus analyzers allow Ethernet connections to be leveraged for remote error monitoring and diagnosis. Jammer and exerciser functionality within a PCIe analyzer enables the same hardware to perform multiple test processes efficiently.
The deep packet inspection of the protocol analyzer is complimented by the inline error injection of the jammer to test recovery times. For users seeking to attach their own DMA and bridge subsystem—for preserving their driver and application software investment, or to customize or optimize functionality using intimate knowledge of the end application—options are available to bypass DMA in the integrated blocks that contain it.
PCIE4C blocks support up to 16 lanes at Gen3 or up to 8 lanes at Gen4 and can be configured for lower link widths and speeds to conserve resources and power. Expanded number of tags to support more requests, enabling improvements in overall system performance. Integrated MSI-X tables. See Product Guide PG for more details. See Product Guide PG for further details. See Product Guide PG for more information.
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